1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) apparatus of active matrix type that displays gray scale and more particularly to a drive apparatus for producing a drive voltage on data lines of a display panel.
2. Related Art
A liquid crystal display (LCD) of the active matrix type having the construction schematically shown in FIG. 1 is known. The LCD comprises a display panel 1, a scan circuit 2, a drive circuit 3, a data source 4 and a ramp generator 5. The display panel 1 is equipped with a plurality of gate lines 6a through 6m and a plurality of data lines 7a through 7n arranged in a matrix form. At each of the crossing points of these gate lines and data lines, a thin film transistor (TFT) device and a pixel electrode are mounted. The drive circuit 3 is a so-called digital-analog type circuit. The drive circuit 3 comprises a plurality of sections corresponding to the plurality of data lines. Each section receives gray scale data concerning one pixel from the data source 4. It also receives a ramp signal (staircase waveform), which repetitively indicates a plurality of voltage levels corresponding to a plurality of gray scales, from the ramp generator 5. Each section selects a voltage level corresponding to the gray scale data and applies it to a corresponding data line. At the same time, the scan circuit 2 successively supplies the gate lines 6a through 6m with a gate pulse that continues for a predetermined time in synchronization with the ramp signal. The TFT selected by the gate pulse applies the voltage level of the data line to the pixel electrode associated with it to charge the liquid crystal electrostatic capacitance thereby, thus providing a gray scale display.
Each drive circuit section has a data latch 10, a decoder 11, a sample hold circuit 12 and a buffer 13, as schematically shown in FIG. 2. The gray scale data for one pixel held in the data latch 10 comprises bits in the number corresponding to the number of gray levels. In case of 16 gray scales, for example, the gray scale data comprises 4 bits. Then the ramp signal Vr applied to the line 14 assumes 16 voltage levels. The decoder 11 generates a sampling pulse PG,4 for selecting the ramp voltage level corresponding to the gray scale data under the control of a clock. The sample-and-hold circuit 12 causes the switch Sw to conduct electricity in accordance with the sampling pulse to hold the specific voltage level in the capacitor C. The voltage level sampled and held in this way is applied to the data line 7a via a buffer 13.
Although the above described scheme realizes gray scale display with up to 16 gray scale levels, it is desired to display a greater number of gray levels. However, the digital-analog type drive has two problems that impede an appropriate increase of gray levels with respect to the sample-and-hold circuit.
First of all, since a shift or an error in the timing of sample hold is reflected as an error in the output voltage, there is a problem in that the error gets ever more serious with an increase in the number of gray levels. In order to clarify this point, reference is made to FIG. 3 showing a timing relation between the gray scale signal portion and the sampling pulse. Vra is, for example, a ramp signal for 64-level grey scale display. When the ramp signal Vra is sampled with the sampling pulse Ps, the presence of an error .DELTA.t in timing, as shown in FIG. 3, generates an error .DELTA.Vo with the result that a gray scale value different from the desired gray scale value will be displayed. As a countermeasure against this problem, it is theoretically possible to reduce the timing error .DELTA.t by improving the external clock that forms the timing basis for the generation of sampling pulses. Such improvement is not easy. In addition, when the number of gray levels is large, a considerable output voltage error still appears even if .DELTA.t is made smaller.
There is another problem concerning the width (duration time) of sampling pulses. Referring to FIG. 3, the width of the sampling pulse Ps meets the step of ramp signal Vra. When the sampling time that follows such pulse is shorter than the time required for appropriately charging the capacitor C of the sample hold circuit 12, there is a possibility that the specific voltage level of the ramp signal cannot be accurately sampled and held, thereby resulting in an error in output voltage.
It is apparent that the above problems become more and more serious with an increase in the number of gray levels, whereby an accurate gray scale display becomes more and more difficult to achieve. Therefore the main object of the present invention is to attain a greater number of gray levels in a liquid crystal display LCD apparatus of active matrix type by eliminating the above problems.
Another object of the present invention is to provide a LCD drive apparatus that can produce an output voltage with less error on the data line of the display panel even if the number of gray levels increases.
A liquid crystal display apparatus of the active matrix type in accordance with the present invention has a liquid crystal panel with a plurality of gate lines and a plurality of data lines arranged in a matrix form, a scan means for successively producing scan signals on said plurality of gate lines, and drive means for producing output signals for gray scale display on said plurality of data lines in synchronization with said scan signals, and characterized in that the drive means comprises:
ramp generator means for generating a plurality of ramp signals in parallel, said ramp signals having waveforms which respectively assume a plurality of voltage levels and are successively shifted by a predetermined amount to entirely assume the total number of voltage levels corresponding to the number of gray levels; and PA1 selector means connected to said ramp generator means and responsive to gray scale data corresponding to each of said data lines for selecting one of said ramp signals and to provide said selected voltage level as an output signal on the corresponding data line.